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1 of 11 070505 features converts cmos sram into nonvolatile memory unconditionally write-protects sram when v cc is out of tolerance automatically switches to battery backup supply when v cc power failure occurs monitors voltage of a lithium cell and provides advanced warning of impending battery failure signals low-battery condition on active low battery warning output signal automatic v cc power-fail detection for 3.0v or 3.3v power supplies space-saving 8-pin dip and soic packages optional 16-pin soic and 20-pin tssop versions reset processor when power failure occurs and hold processor in reset during system power-up industrial temperature range of -40c to +85c pin assignment pin description v cci - power supply input v cco - sram power supply output v bat - backup battery input cei - chip enable input ceo - chip enable output tol - v cc tolerance select bw - battery warning output (open drain) rst - reset output (open drain) gnd - ground nc - no connection description the ds1314 nonvolatile controller with battery monitor is a cmos circuit which solves the application problem of converting cmos ram into nonvolatile memory. incoming power is monitored for an out- of-tolerance condition. when such a condition is detected, chip enable is inhibited to accomplish write protection and the battery is switc hed on to supply the ram with uninterrupted power. special circuitry uses a low-leakage cmos process which affords precise voltage detection at extremely low battery consumption. ds1314 3v nonvolatile controller with lithium battery monito r www.maxim-ic.com 1 2 3 4 20 19 18 17 5 6 7 8 9 10 11 12 13 14 15 16 nc v cci rst nc nc bw nc ceo nc cei nc v cco nc v bat nc nc tol nc nc gnd ds1314e 20-pin tssop 1 2 3 4 8 7 6 5 gnd tol v bat v cco v cci bw ceo cei ds1314s-2 8-pin soic (150-mil) 1 2 3 4 8 7 6 5 gnd tol v bat v cco v cci bw ceo cei ds1314 8-pin dip (300-mil) 1 2 3 4 16 15 14 13 5 6 7 89 10 11 12 nc v cco nc v bat nc tol nc gnd nc v cci rst nc bw ceo nc cei ds1314s 16-pin soic (300-mil)
ds1314 2 of 11 in addition to battery-backup support, the ds1314 pe rforms the important function of monitoring the remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life. because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority of its life, accurate battery monitoring requires loaded-battery voltage measurement. the ds1314 performs such measurement by periodically comparing th e voltage of the battery as it supports an internal resistive load with a carefully selected reference vo ltage. if the battery voltage falls below the reference voltage under such conditions, the battery will soon reach end-of-life. as a result, the battery warning pin is activated to signal the need for battery replacement. memory backup the ds1314 performs all the circuit f unctions required to provide batte ry-backup for an sram. first, the device provides a switch to direct power from the battery or the system power supply (v cci ). whenever v cci is less than the switch point v sw and v cci is less than the battery voltage v bat , the battery is switched in to provide backup power to the sram. this switch has vo ltage drop of less than 0.2 volts. second, the ds1314 handles power failure de tection and sram write protection. v cci is constantly monitored, and when the supply goes out of toleran ce, a precision comparator detects power failure and inhibits chip enable output ( ceo ) in order to write-protect the sram. this is accomplished by holding ceo to within 0.2 volts of v cco when v cci is out of tolerance. if cei is (active) low at the time that power failure is detected, the ceo signal is kept low until cei is brought high again. once cei is brought high, ceo is taken high and held high until after v cci has returned to its nominal voltage level. if cei is not brought high by 1.5 s after power failure is detected, ceo is forced high at that time. this specific scheme for delaying write protection for up to 1.5 s guarantees that any memory access in progress when power failure occurs will complete properly. power failure detection occurs at 3.0v nominal (3.3v supply) when the tol pin is wired to gnd or at 2.7v nominal (3.0v supply) when tol is connected to v cco . battery voltage monitoring the ds1314 automatically performs periodic battery voltage monitoring at a factory-programmed time interval of 24 hours. such monitoring begins within t rec after v cci rises above v cctp , and is suspended when power failure occurs. after each 24-hour period (t btcn ) has elapsed, the ds1314 connects v bat to an internal 1.2 m test resistor (r int ) for one second (t btpw ). during this one second, if v bat falls below the factory- programmed battery vo ltage trip point (v btp ), the battery warning output bw is asserted. while bw is active battery testing will be performed with period t btcw to detect battery removal and replacement. once asserted, bw remains active until the battery is physically removed and replaced by a fresh cell. the battery is still re-tested after each v cc power-up, however, even if bw was active on power-down. if the battery is found to be higher than v btp during such testing, bw is deasserted and regular 24-hour testing resumes. bw has an open-drain output driver. battery replacement following bw activation is normally done with v cci nominal so that sram data is not lost. during battery replacement, the minimum time duration between old battery detachment and new battery attachment (t bdba ) must be met or bw will not deactivate following attachment of the new battery. should bw not deactivate for this reason, the new battery can be detached for t bdba and then re- attached to clear bw .
ds1314 3 of 11 note: the ds1314 cannot constantly monitor an att ached battery because such monitoring would drastically reduce the life of the battery. as a resu lt, the ds1314 only tests the battery for one second out of every 24 hours and does not monitor the battery in any way between tests. if a good battery (one that has not been previously flagged with bw ) is removed between battery tests, the ds1314 may not immediately sense the removal and may not activate bw until the next scheduled battery test. if a battery is then reattached to the ds1314, the battery ma y not be tested until th e next scheduled test. note : battery monitoring is only a useful technique when testing can be done regularly over the entire life of a lithium battery. because the ds1314 only performs battery monitoring when v cc is nominal, systems which are powered-down for excessively long periods can completely drain their lithium cells without receiving any advanced warning. to prev ent such an occurrence, systems using the ds1314 battery monitoring feature should be powered-up periodi cally (at least once every few months) in order to perform battery testing. furthermore, anytime bw is activated on the first battery test after a power-up, data integrity should be checked via checksum or other technique. power monitoring ds1314s and ds1314e varieties have an additional reset pin. these va rieties detect out-of-tolerance power supply conditions and warn a processor-based system of impending power failure. when v cci falls below the trip point level defined by the tol pin (v cctp ), the v cci comparator activates the reset signal rst . reset occurs at 3.0v nominal (3.3v supply) wh en the tol pin is connected to gnd or at 2.7v nominal (3.0v supply) when tol is connected to v cco . rst also serves as a power-on reset during power-up. after v cci exceeds v cctp , rst will be held active for 200 ms nominal (t rpu ). this reset period is sufficiently lo ng to prevent system operation during power-on transients and to allow t rec to expire. rst has an open-drain output driver. freshness seal mode when the battery is first attached to the ds1314 without v cc power applied, the device does not immediately provide battery-backup power on v cco . only after v cci exceeds v cctp and later falls below both v sw and v bat will the ds1314 leave freshness seal mode and provide battery-backup power. this mode allows a battery to be attached during manufacturing but not used until after the system has been activated for the first time. as a result, no battery energy is drained during storage and shipping.
ds1314 4 of 11 functional block diagram figure 1
ds1314 5 of 11 absolute maximum ratings* voltage on any pin relative to ground -0.5v to +7.0v operating temperature -40 c to +85 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (-40c to +85c) parameter symbol min typ max units notes supply voltage tol=gnd v cci 3.0 3.3 3.6 v 1 supply voltage tol=v cco v cci 2.7 3.0 3.3 v 1 battery supply voltage v bat 2.0 6.0 v 1 logic 1 input v ih 2.0 v cci +0.3 v 1, 12 logic 0 input v il -0.3 +0.8 v 1, 12 dc electrical characteristics (-40c to +85c; v cci = v cctp ) parameter symbol min typ max units notes operating current (ttl inputs) i cc1 50 200 a 2 operating current (cmos inputs) i cc2 30 100 a 2, 5 ram supply current (v cco v cci -0.2v) i cco1 80 ma 3 ram supply current (v cco v cci -0.3v) i cco1 140 ma 4 v cc trip point (tol=gnd) v cctp 2.8 2.9 3.0 v 1 v cc trip point (tol=v cco ) v cctp 2.5 2.6 2.7 v 1 v bat trip point v btp 2.5 2.6 2.7 v 1 v cc /v bat switch point (tol=gnd) v sw 2.6 2.7 2.8 v 1 v cc /v bat switch point (tol= v cco ) v sw 2.4 2.5 2.6 v 1 output current @ 2.2v i oh -1 ma 7, 10 output current @ 0.4v i ol 4 ma 7, 10 input leakage i il -1.0 +1.0 a output leakage i lo -1.0 +1.0 a battery monitoring test load r int 0.8 1.2 1.5 m ? dc electrical characteristics (-40c to +85c; v cci < v bat ; v cci < v sw ) parameter symbol min typ max units notes battery current i bat 100 na 2 battery-backup current i cco2 500 a 6 supply voltage v cco v bat -0.2 v 1 ceo output v ohl v bat -0.2 v 1, 8
ds1314 6 of 11 capacitance (t a =25c) parameter symbol min typ max units notes input capacitance ( cei , tol) c in 7 pf output capacitance ( ceo , bw , rst ) c out 7 pf ac electrical characteristics (-40c to +85c; v cci v cctp ) parameter symbol min typ max units notes cei to ceo propagation delay t pd 12 20 ns ce pulse width t ce 1.5 s 11 v cc valid to end of write protection t rec 12 125 ms 9 v cc valid to cei inactive t pu 2 ms v cc valid to rst inactive t rpu 150 200 350 ms 10 v cc valid to bw valid t bpu 1 s 10 ac electrical characteristics (-40c to +85c; v cci < v cctp ) parameter symbol min typ max units notes v cc slew rate t f 150 s v cc fail detect to rst active t rpd 5 15 s 10 v cc slew rate t r 150 s ac electrical characteristics (-40c to +85c; v cci v cctp ) parameter symbol min typ max units notes battery test to bw active t bw 1 s 10 battery test cycle-normal t btcn 24 hr battery test cycle-warning t btcw 5 s battery test pulse width t btpw 1 s battery detach to battery attach t bdba 7 s battery attach to bw inactive t babw 1 s 10
ds1314 7 of 11 timing diagram: power-up note: if v bat < v sw , v cco will begin to slew with v cci when v cci = v bat .
ds1314 8 of 11 timing diagram: power-down note: if v bat < v sw , v cco will slew down with v cci until v cci = v bat .
ds1314 9 of 11 timing diagram: battery warning detection note: t bw is measured from the expiration of the internal timer to the activation of the battery warning output bw . timing diagram: battery replacement
ds1314 10 of 11 notes: 1. all voltages referenced to ground. 2. measured with outputs open circuited. 3. i cco1 is the maximum average load which the ds1314 can supply to attached memories at v cco v cci -0.2v. 4. i cco1 is the maximum average load which the ds1314 can supply to attached memories at v cco v cci -0.3v. 5. all inputs within 0.3v of ground or v cci . 6. i cco2 is the maximum average load current which the ds1314 can supply to the memories in the battery-backup mode. 7. measured with a load as shown in figure 2. 8. chip enable output ceo can only sustain leakage current in the battery-backup mode. 9. ceo will be held high for a time equal to t rec after v cci crosses v cctp on power-up. 10. bw and rst are open drain outputs and as such cannot source current. external pull-up resistors should be connected to these pins for proper operation. both bw and rst can sink 10 ma. 11. t ce maximum must be met to ensu re data integrity on power-down. 12. in battery-backup mode, inputs must never be below ground or above v cco . dc test conditions outputs open all voltages are referenced to ground ac test conditions output load: see below input pulse levels: 0 - 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns output load figure 2 * including scope and jig capacitance
ds1314 11 of 11 data sheet revision summary the following represent the key differences betw een 12/16/96 and 06/12/97 version of the ds1314 data sheet. please review this summary carefully. 1. changed v bat max to 6v. 2. changed v cctp values to 2.8 - 3.0v (tol = gnd) and 2.5 - 2.7v (tol = v cc ). 3. changed t babw from 7s to 1s max. 4. changed block diagram to show u l compliance. the following represent the key differences betw een 06/12/97 and 08/29/97 version of the ds1314 data sheet. please review this summary carefully. 1. changed ac test conditions. 2. changed t pd to 20 max & 12 typ. the following represent the key differences betw een 08/29/97 and 12/16/97 version of the ds1314 data sheet. please review this summary carefully. 1. changed v cci mins from 3.05v to 3.0v (tol=gnd) and from 275v to 2.7v (tol=v ccd ) (this should have been done on 06/12/ 97 revision but was overlooked). 2. specified input capacitance as being only for cei , tol and output capacitance as being only for ceo , bw and rst . this is not a change but rather clarification. 3. removed ?preliminary? from title bar.

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